(1) Field of the Invention
The invention relates to a digital circuit, and, more particularly, to a data sampling circuit having dynamically adjustable setup/hold times.
(2) Description of the Prior Art
Data sampling circuits are widely used in the art of digital circuits. In a data sampling circuit, the state (high or low) of a data signal is captured at a periodic time point coincident with a clocking signal. Referring now to FIG. 1, an exemplary data sampling circuit 10 is illustrated in schematic form. In the circuit 10 an input signal DATA 14 is processed through two signal paths, DATAPATH1 and DATAPATH2. DATAPATH1 includes two inverter buffers 42 and 46 that generate the internal signal data1 26. DATAPATH2 includes two inverter buffers 54 and 58 that generate the internal signal data2 30. Inverter buffers are used so that the input signal DATA 14 need only drive the capacitive load of the first inverter buffers 42 and 54 and the short line routings from the DATA 14 input to those buffers. Registers REG1 50 and REG2 62 are used to periodically sample data1 26 and data2 30 based on the system clock CLK 66. REG1 50 samples data1 26 at the rising edge of CLK 66 to generate the sampled output DATA_OUT1 34. By contrast, REG2 62 samples data2 30 at the falling edge of CLK 66 to generate the sampled output DATA_OUT2 38.
The timing performance of the sampling circuit 10 is also shown. The data1 signal 26 and the data2 signal 30 follow the DATA input 14. DATA_OUT1 34 and DATA_OUT2 38 follow data1 26 and data2 30, respectively. However, the DATA_OUT1 signal 34 changes on the rising edges of the system clock CLK 66, while the DATA_OUT2 signal 38 changes on the falling edges of the system clock CLK 66. Several key timing specifications 70, 72, 74, and 78 are noted. For the DATA signal 14 to be properly sampled by the sampling registers REG1 50 and REG2 62, the signal state 14 must be constant for a window of time around the sampling edge of the clock CLK 66. This sampling window is commonly defined as the setup and hold window for the signal. That is, the DATA 14 state must be setup a certain time before the sampling edge of CLK 66 and must be held a certain time after the sampling edge of CLK 66 to be certain that the state is sampled correctly. In this case, the data setup time at a rising edge, tsr 70, and the data hold time at a rising edge of the clock, thr 74, are critical parameters for generating DATA_OUT1 from DATA 14 via rising edge sampling. Likewise, the data setup time at a falling edge, tsf 72, and the data hold time at a falling edge of the clock, thf 78, are critical parameters for generating DATA_OUT2 from DATA 14 via falling edge sampling.
In most cases, the DATA signal 14 is not perfectly synchronized with the system clock CLK 66. As a result, the timing locations of edge transitions for DATA 14 can occur at very close to the sampling edges (rising or falling) of CLK 66. As a result, the specified setup and hold times 70, 72, 74, and 78 may be violated and may further result in data mis-sampling. It should be noted that the inverting buffers 42, 46, 54, and 58 create fixed delays between DATA and either DATA1 26 and DATA2 30. Therefore, any assistance in meeting a setup/hold timing that is derived from the inverting buffers 42, 46, 54, and 58, such as holding a signal state longer for a sampling edge, is lost if the relative position of the DATA 14 edges with respect to CLK 66 changes. A method to dynamically adjust the setup and hold timings of the digital sampling circuit is therefore a key objective of the present invention.
Several prior art inventions relate to input buffers and to data paths. U.S. Pat. No. 6,411,150 to Williams teaches an input buffer having a dynamically controlled switching threshold. A register is used to store a programmed state for the input buffer. Switches in the buffer circuit control the switching threshold. These switches are activated or de-activated based on the register state. U.S. Pat. No. 5,506,534 to Guo et al shows a delay circuit with an adjustable delay. MOS transistors, operating as large value resistors, are turned ON or OFF to adjust the delay. U.S. Pat. No. 6,650,190 to Jordon et al shows a ring oscillator circuit having adjustable delay elements. A fine boost control signal is provided to each delay cell to adjust the delay via the gate voltage on MOS load devices. U.S. Pat. No. 4,618,788 to Backes et al teaches an adjustable delay circuit for an integrated circuit device.